1. Field of the Invention
The present invention relates generally to a method and system for synthesizing a circuit design. More particularly, the invention relates to a method and system for concurrently synthesizing different parts of a circuit design by using budgeting technics to perform the timing and logic design rules constraints allocation.
2. State of the Art
Most conventional synthesis tools available to designers are able to handle circuit designs whose size can be up to 100,000 gate equivalents. A designer working on a chip with greater that 100,000 gate equivalents has to manually partition the circuit design into smaller pieces (e.g., sub-blocks) in order for conventional synthesis tools to operate on the entire circuit design. A design with sub-blocks is also referred to as a hierarchical design. Partitioning the circuit design into small sub-blocks is a common procedure for designers and allows conventional synthesis tools to synthesize the entire circuit design.
However, in the above procedure, it is difficult to derive the timing and logic design rules constraints from the top-level of the chip into budgeted local constraints applied to the sub-blocks. The budgeted constraints are the result of an allocation which foresees the nominal timing performance of the sub-blocks. The allocation of timing and logic design rules budgets is mandatory in order to load the sub-blocks in the synthesis tools and run several sub-block synthesis (eventually in parallel) instead of one full synthesis run on the whole design.
The operation of deriving global constraints into local constraints applied to a sub-block is referred to as the characterization of the corresponding sub-block. The operation of deriving the global constraints into budgeted local constraints is referred to as the timing and logic design rules constraints allocation.
The timing and logic design rules constraints allocation of a sub-block are useful when a team leader would like to assign each of his engineers to the synthesis of one sub-block. The engineers will work in parallel and each of them will need the timing and logic design rules constraint of his respective sub-block. In this situation, the timing and logic design rules constraints allocation of the sub-blocks should provide the scripts of the synthesis. As a result, this operation has to be done before the synthesis itself.
For a more detailed discussion of the above situation with respect to RTL Floorplanner tools, reference is made to co-pending U.S. application Ser. No. 08/921,361, titled "Method and System for Floorplanning a Circuit Design at a High Level of Abstraction," filed on Aug. 29, 1997, the content of which is hereby incorporated by reference in its entirety.